This invention relates to the reception of encoded signals employing decision feedback equalization. It is particularly though not necessarily exclusively concerned with the reception of data in the form of data packets in Ethernet or ATM data communications systems, particularly dual systems capable of operating at different frequencies such as both 10 MHz and 100 MHz.
In particular the invention is intended for use with the Ethernet local area standard in which an analog carrier signal of constant frequency has its amplitude modulated in accordance with a binary digital bit stream to be encoded. The amplitude variation applied to the analog carrier signal provides three amplitude levels, known as xe2x88x921, 0 and +1 respectively, represented by a negative voltage related to a datum level, the datum level and a positive voltage relative to the datum level. Typically, a binary 0 is represented by the occurrence of two consecutive similar symbols, namely the occurrence of the same carrier amplitude in one symbol period as in the previous symbol period and a binary 1 is represented by a change from one symbol to another.
Data signals, particularly those having more than two possible states and therefore more than one decision level, such as partial response signals or, particularly, Ethernet signals wherein the intended levels are xe2x88x921, 0 and +1, suffer in transmission over most practical channels dispersion exhibited by both base line wander and inter-symbol interference. It is customary to provide, for example for each port of a device in an Ethernet system, a receiver which includes equalization, to compensate for the dispersion of the incoming signal in the transmission medium coupled to the port, and subsequent analog-to-digital conversion. It will be understood that these actions are associated with the xe2x80x98physical layerxe2x80x99 or layer 1 of the OSI model. There is an increasing trend towards integration of multiple ports in Ethernet devices and accordingly, for such devices to remain reasonably priced, it is desirable to minimize the area on a silicon chip occupied by the physical layer devices for any channel and to minimize the associated power consumption.
As is generally well known in the art, a decision feedback equalizer basically operates to provide a feedback signal representing an estimate of inter-symbol interference. Typically it comprises a multiply tapped transversal filter through which the decoded data is sequentially shifted. Individual decoded symbol values available at the taps are multiplied by respective coefficients and the products are summed to construct the estimate of the inter-symbol interference present in the received signal. This estimate is algebraically combined with the received signal before the latter is subject to analog-to-digital conversion so as to shift the received signal relative to the decision levels provided by the analog-to-digital converter.
The actual inter-symbol interference is represented by a convolution of the impulse response of the transmission path and the data passing through it. In practice it is necessary to presume initially a set of coefficients from a probability density function calculated by assuming that the input signal is represented by a pseudo-random sequence. It is then desirable to adapt the coefficient using some appropriate algorithm whereby the coefficients are adjusted to provide a measure of inter-symbol interference related to the particular data patterns being employed.
United States patent specification U.S. Pat. No. 5,157,690 describes an adaptive convergent decision feedback equalizer in which the coefficients and the products of the coefficients and the estimated inter-symbol interference are computed digitally.
United States patent specification U.S. Pat. No. 5,581,585 describes an analog clock timing recovery circuit including a decision feedback equalizer. It briefly describes the xe2x80x98least mean squaresxe2x80x99 algorithm and briefly discusses the xe2x80x98least squaresxe2x80x99 and xe2x80x98recursive least squarexe2x80x99 algorithms for adapting the coefficients generated by the feedback equalizer.
United States patent specification U.S. Pat. No. 5,604,741 describes an Ethernet receiver including a three level data slicer of which the output provides symbols for a decision feedback equalizer.
Broadly, there are two techniques available for the reception of signals transmitted over a physical medium according, for example, to the well known 100 BASE-TX standard. A first is in effect an all-analog receiver wherein equalization is performed in the analog domain. A second technique is, in effect, an all digital receiver which though having some necessary analog components, such as an analog receiver before a gain control stage, performs equalization in the digital domain.
An analog receiver typically comprises an analog low pass filter coupled to a gain control stage of which the output is coupled to an analog equalizer. The output of the analog equalizer is coupled to an analog phase lock loop so as to provide recovery of a data clock required both for digital processing of the received signals and for the clocking of an analog-to-digital converter which may convert the input signal, after equalization, into a binary, non-return to zero, form. The output of the analog equalizer also provides a control signal for a gain control circuit operating the gain control stage aforementioned. Broadly speaking, such receivers require quite a complex analog filter and a complex analog equalizer. Inter-symbol interference, offset and noise are difficult to minimize; these difficulties increase at higher operating frequencies.
A typical xe2x80x98digitalxe2x80x99 receiver for use in a similar context likewise has a fixed analog filter at its front end, the filter being coupled to a gain control stage of which the output is coupled to the input of a multiple level flash analog-to-digital converter. Typically for a 100 MHz system the flash converter operates at least 125 MHz and provides sixty-four levels of analog-to-digital conversion. The flash converter is coupled to the input of a digital equalising filter of which the output is coupled to a digital clock recovery circuit and to a digital automatic gain control circuit. The latter drives a digital-to-analog converter which provides the gain control signal for the aforementioned gain control stage. The digital clock recovery circuit provides a control signal for a voltage controlled oscillator which provides a recovered clock signal used in the further digital processing of the received signal and also to control the clocking of the flash converter. The final sum of the products of the previously decoded symbol values and the respective coefficients are applied to the digital representation of the input signal. Broadly, a receiver on these lines is expensive in terms of occupied chip area and power consumption.
Digital equalizers of the kind mentioned are commonly decision feedback equalizers wherein a decision or slicing level is adjusted according to a weighted sum of the values of a multiplicity of earlier received signals, the weighting being adjusted according to a suitable adaptive algorithm. Several algorithms are known for this purpose. Generally preferred is the xe2x80x98least mean squaresxe2x80x99 algorithm originally described by B Widrow. In an all digital domain, the weighting or coefficients of the previous symbols and the multiplication of the weighted values must all be performed digitally, the digital circuit operating necessarily at the symbol rate. Such a practice is expensive both in terms of area of silicon employed and power consumed.
The present invention is based on a hybrid system in which decision feedback equalization is performed by digital computation of coefficients, the conversion of those coefficients into analog form and the adjustment or equalization of the input signal in the analog domain. Broadly, in comparison with known digital systems, a system according to the invention requires many fewer fast comparators and much less fast circuitry (i.e. digital circuitry operating at or above the symbol rate) and a reduction in quantisation noise. It is moreover much easier to obtain accurate digital-to-analog conversion than analog-to-digital conversion.
Reference will hereinafter be made to the accompanying drawings, to indicate both how the invention may be put into practice and to indicate various further features of the invention.